1. Field of the Invention
The present invention relates generally to phase-locked loops (PLLs) and voltage-controlled oscillators (VCOs) used in the PLLs, and more particularly, to a balanced interleaved feedforward VCO (BIFFVCO).
2. Description of the Related Art
High-frequency voltage-controlled oscillators (VCOs) are extremely important for applications such as processor clock generation and/or distribution, wired and/or wireless communication, system synchronization, and frequency synthesis. Research on VCos for the past decade has been concentrated in the areas of high frequency, lower jitter, lower operating voltage and power, and increasing the frequency tuning range. Many of these design goals are achieved only at the expense of some or all of the other performance objectives. As technology progresses toward shorter channel lengths and lower operating voltages, the headroom available for an analog design decreases to the point that cascading (stacking) is no longer feasible. High-frequency analog VCOs operating with properly biased current sources may have signal swings that are only a small fraction of the supply voltage, severely limiting their usefulness.
Current-starved ring-oscillators using 3 or 4 levels of stacking have become quite common, but they have extreme sensitivity to noise due to very high gain, are inherently nonlinear (especially near cutoff, where they often stop oscillating), are inherently limited to 2X max frequency range and are difficult to build in less than 4 levels. Multiphase oscillators offer advantages by pipelining operations using equally spaced phases at lower frequencies, but control mechanisms in delay interpolators introduce offsets from the ideal spacing. LC-based oscillators are capable of high frequency and extremely low jitter but are difficult to integrate and model and have tuning ranges of only a few percent.
Therefore, there is a need for a VCO that creates a frequency dither that is symmetric about a DC operating point and that interfaces directly to a common phase-frequency detector, resulting in more optimal PLL performance.
The present invention provides an oscillator system, which has a plurality of delay paths coupled in a loop. The oscillator system also has an AC feedforward path coupled in parallel with one or more delay paths in the loop. The AC feedforward path includes first and second parallel sections. The first parallel section has a plurality of parallel branches and is configured for receiving one or more control signals. The plurality of parallel branches is selectively conducted in response to the one or more control signals.
The second parallel section is coupled in series with the first parallel section and is configured to remain conducting when any of the plurality of parallel branches becomes conducting. The first and second parallel sections are configured to transmit an AC feedforward signal when conducting.